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TESTING DIGITAL LOGIC CIRCUITS
Exam II
Due: 4/7/2016

Name: ________________________________________
1. A combinational circuit has 6 inputs (a, b, c, d, e, f, g) and 4 outputs:
z1(a, b, c, d), z2(b, d, e), z3(c, e, f), z4(a, d, f), z5(a, c, g). Find:
(a) The dependency matrix D.
(b) The minimum number of test inputs needed to test the circuit pseudoexhaustively
(c) Give the tests to be applied in terms of circuit inputs (a,b,c,d,e,f,g)

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2. In the circuit given below, assuming that all flip-flops are connected
to form a scan chain in the order 5,6,7, determine a test for a slow to
fall fault on line 16 (a) using launch off shift test method and (b)
launch off capture test method assuming that the circuit inputs 1,2,3,
and 4 are to be held constant during the two capture cycles.

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3. The following composite table represents a fault-free machine M and
machine M1 with a fault f1. Assume that both the machines start in an
unknown initial state. Find a test sequence (if one exists) that detects
the fault f1.
x=0
A
B
C
D
E
F

x=1

B,0
D,1
F,1
F,1
F,1
C,0/1

B,1
A,0
D,1
E,0
C,0
E,0

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4. Find a self-initializing input sequence (if it exists) to detect line 14 stuck-at-0.
For this circuit 1, 2, 3, 4 are the primary inputs, 5, 6 and 7 are present state variables
q1, q2, q3 and 15, 24 and 25 are the next state variables Q1, Q2 and Q3 respectively.
(All flip-flops in this circuit are D-flip-flops. The combinational part of this circuit is
given below).

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5. Determine tests to detect the four way bridging faults between lines m and
j. If for some fault(s) tests do not exist give reasons.

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